The present invention relates to a method of testing semiconductor memory devices such as., an EEPROM (electrically erasable programmable ROM) and an EPROM (erasable programmable ROM). More specifically, the invention relates to an accelerated testing method of the data-holding capability of semiconductor memory devices.
In general, it is assured that semiconductor memory devices such as an EEPROM have a capability of holding written data for at least a specified time. For example, a data-holding time of 10 years in an atmosphere of 70.degree. C. is assured. However, since it is not practical to perform, in a semiconductor manufacturing process, a test of placing a semiconductor memory device in a 70.degree. C. atmosphere for 10 years to confirm a satisfactory data-holding ability, an accelerated data-holding test is conventionally performed in which a semiconductor memory device is subjected to a baking treatment.
Referring to FIG. 2, an example of a procedure of the accelerated test is described below.
First, in a semiconductor substrate (hereinafter referred to simply as "wafer") measurement step N1, electrical characteristics of memory devices, which have been formed on the wafer in a wafer production process, are measured. In an assembling step N2, the wafer is cut into pieces of individual memory devices, which are then subjected to die bonding and wire boding and finally sealed using a resin or the like. In measurement step 1 (step N3), electrical characteristics of the packaged semiconductor memory device are evaluated. In this measurement step 1, data for an accelerated data-holding test (hereinafter referred to simply as "test data") are written into the semiconductor memory device.
In a baking step N4, the semiconductor memory device, in which the test data have been written, is subjected to a baking treatment for the accelerated test. In the baking treatment, for example, the semiconductor memory device is placed in an atmosphere of 150.degree. C. for 143 hours. After the baking treatment, it is checked in measurement step 2 (step N5) whether the test data are held in the semiconductor memory device in a correct manner. Then, the semiconductor devices which have passed the tests are shipped.
However, the above-described conventional testing method has the following problems:
1) Because of the limitations of, for instance, heat resistance of the resin to be used for sealing the semiconductor memory device the temperature of the baking treatment atmosphere is restricted to a relatively low value. Therefore, although the term "accelerated test" is used, a relatively long period is required for the baking treatment, which causes a low operational efficiency.
2) In order to baking a large number of packaged semiconductor memory devices at one time, a large-scale heat treatment apparatus and a wide space for accommodating it are required.
3) When the packaged semiconductor memory device is placed in a high-temperature atmosphere for a long time, the thermal expansion etc. of the sealing resin will impose an undesired stress on the internal device and ultra-thin wires (e.g., gold wires), which may cause a reduction of a reliability of the semiconductor memory device. Further, oxidized lead terminals will become difficult to be soldered.